絲?。?strong>MAT；Package：DO-214AC；400W Transient Voltage Suppressor (TVS) protection device

Description and applications This device has the ability to clamp dangerous high voltage, short term transients such as produced by directed or radiated electrostatic discharge phenomena before entering sensitive component regions of a circuit design. Response time of clamping action is virtual

文件：489.87 Kbytes 頁數(shù)：6 Pages

MICROSEMI

美高森美

MANUAL PHASE ANGLE TRIAC TRIGGER MODULE

FEATURES ? Compact and easy to use ? Solid state reliability ? Single hole panel mounting ? Minimum offset ? Highly efficient

文件：56.45 Kbytes 頁數(shù)：1 Pages

UNITEDAUTOMATION

Matched Monolithic Dual Transistor

GENERAL DESCRIPTION The MAT01 is a monolithic dual NPN transistor. An exclusive silicon nitride triple passivation process provides excellent stability of critical parameters over both temperature and time. Matching characteristics include offset voltage of 40 μV, temperature drift of 0.15 μV/°

文件：119.82 Kbytes 頁數(shù)：8 Pages

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亞德諾

Matched Monolithic Dual Transistor

GENERAL DESCRIPTION The MAT01 is a monolithic dual NPN transistor. An exclusive silicon nitride triple passivation process provides excellent stability of critical parameters over both temperature and time. Matching characteristics include offset voltage of 40 μV, temperature drift of 0.15 μV/°

文件：261.459 Kbytes 頁數(shù)：12 Pages

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亞德諾

Matched Monolithic Dual Transistor

FEATURES Low VOS (VBE match): 40 μV typical, 100 μV maximum Low TCVOS: 0.5 μV/°C maximum High hFE: 500 minimum Excellent hFE linearity from 10 nA to 10 mA Low noise voltage: 0.23 μV p-p from 0.1 Hz to 10 Hz High breakdown: 45 V min APPLICATIONS Weigh scales Low noise, op amp, front end C

文件：235.33 Kbytes 頁數(shù)：12 Pages

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亞德諾

Matched Monolithic Dual Transistor

FEATURES Low VOS (VBE match): 40 μV typical, 100 μV maximum Low TCVOS: 0.5 μV/°C maximum High hFE: 500 minimum Excellent hFE linearity from 10 nA to 10 mA Low noise voltage: 0.23 μV p-p from 0.1 Hz to 10 Hz High breakdown: 45 V min APPLICATIONS Weigh scales Low noise, op amp, front end C

文件：235.33 Kbytes 頁數(shù)：12 Pages

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亞德諾

Matched Monolithic Dual Transistor

FEATURES Low VOS (VBE match): 40 μV typical, 100 μV maximum Low TCVOS: 0.5 μV/°C maximum High hFE: 500 minimum Excellent hFE linearity from 10 nA to 10 mA Low noise voltage: 0.23 μV p-p from 0.1 Hz to 10 Hz High breakdown: 45 V min APPLICATIONS Weigh scales Low noise, op amp, front end C

文件：235.33 Kbytes 頁數(shù)：12 Pages

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亞德諾

Matched Monolithic Dual Transistor

GENERAL DESCRIPTION The MAT01 is a monolithic dual NPN transistor. An exclusive silicon nitride triple passivation process provides excellent stability of critical parameters over both temperature and time. Matching characteristics include offset voltage of 40 μV, temperature drift of 0.15 μV/°

文件：119.82 Kbytes 頁數(shù)：8 Pages

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亞德諾

Matched Monolithic Dual Transistor

FEATURES Low VOS (VBE match): 40 μV typical, 100 μV maximum Low TCVOS: 0.5 μV/°C maximum High hFE: 500 minimum Excellent hFE linearity from 10 nA to 10 mA Low noise voltage: 0.23 μV p-p from 0.1 Hz to 10 Hz High breakdown: 45 V min APPLICATIONS Weigh scales Low noise, op amp, front end C

文件：235.33 Kbytes 頁數(shù)：12 Pages

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亞德諾

Matched Monolithic Dual Transistor

FEATURES Low VOS (VBE match): 40 μV typical, 100 μV maximum Low TCVOS: 0.5 μV/°C maximum High hFE: 500 minimum Excellent hFE linearity from 10 nA to 10 mA Low noise voltage: 0.23 μV p-p from 0.1 Hz to 10 Hz High breakdown: 45 V min APPLICATIONS Weigh scales Low noise, op amp, front end C

文件：235.33 Kbytes 頁數(shù)：12 Pages

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